spic

spic - Simple Priority Interrupt Circuit Core

Overview

spic is a circuit providing interrupt encoding and enable / disable of up to sixteen interrupt sources including nmi. I1 is the highest priority interrupt and I15 is the lowest. It is possible to control the value of all interrupt enables by writing register 1 with the desired enable / disable pattern. Alternately registers two and three can be used to selectively disable and enable specific interrupt enable bits. The encoded value of the highest priority interrupt can be read from register zero. This value has already been shifted left twice to make it easier to use as a table index.

All signals are active high unless otherwise noted.

Download spic.v

Performance values are approximate (Spartan 2e-6):

99LUTs / 55 slices / 141MHz

spic

module spic(rst_i, clk_i, cyc_i, irqo, nmii, nmio, we_i, ack_o, sel_i, adr_i, dat_i, dat_o,
i1, i2, i3, i4, i5, i6, i7,
i8, i9, i10, i11, i12, i13, i14, i15, irqenc);

Signal	Description
rst_i	This signal is normally connected to the system reset signal. It resets the core disabling all interrupts. rst_i is sampled on the positive edge of the clock
clk_i	this is usually connected to the system clock and is used as a base timing clock.
ack_o	This signal indicates the circuit is ready. It is internally tied to the circuit select signal meaning the circuit is ready as soon as it is connected.
irqo	This signal is an irq output to be connected to the processor's irq input.
nmii	This signal is the nmi input
nmio	This signal is the nmi output to be connected to the processor's nmi input
cyc_i	cycle active - this is how the core identifies a valid bus transfer to / from this circuit.
we_i	This signal is used to signify a write operation to the circuit.
sel_i	This is a two bit byte select signal indicating which portions of the 16 bit bus contain valid transfer information
adr_i	This is a two bit address vector used to address one of four available spic registers. (Registers are described below).
dat_i	This is the sixteen bit data input bus to the core.
dat_o	This is the sixteen bit data output bus from the core. It is forced to zero when the core is not selected.
i1 to i15	These are the irq input signals i1 has the highest priority and i15 the lowest.
irqenc	This is a four bit vector indicating the encoded value of the highest priority interrupt. A value of zero means no interrupt is present.

Register Description

Reg. No.	Function	Description
0	current interrupt	read only - this register contains the encoded value of the highest priority interrupting device in bits 5 through 2. The remaining bits of the register are zero. This choice of bits was made to make it easy to use the value in the register as a word index.
1	multi-bit request enable / disable	read / write - this register contains request enable bits for each request line. 1 = request enabled, 0 = request disabled. On reset this register is set to zero (disable all ints). bit zero is specially reserved for nmi. The remaining bits correspond to the level of interrupt.
2	single bit disable request	write only - this register disables the interrupt indicated by the low order four bits of the input data. It is provided as an alternate to setting all values in register 1.
3	single bit enable request	write only - this register enables the interrupt indicated by the low order four bits of the input data. It is provided as an alternate to setting all values in register 1.