© 2003 Bird Computer
Overview
Bc_uart is a uart core that is somewhat unique in that it can use almost any base clock frequency as a timing clock, and run at virtually any desired baud rate, due to the use of a harmonic frequency synthesizer that determines the baud rate.
BC_UART is composed of four modules: bc_uart, bc_uart_rx, bc_uart_tx and bc_fifo16x8. bc_uart uses the BCS SoC bus interface, but is easily adapted to SoC buses.
The bc_uart module contains the baud rate generation logic and glues everything together into a useable uart core. bc_uart_rx contains the receiver logic for the uart, bc_uart_tx contains the uart transmitter logic, bc_fifo16x8 contains the fifo used for the receiver and transmitter modules.
All signals are active high unless otherwise noted.
BC_UART
module bc_uart(reset,
clk, ce, cs, rd, wr, a, di, do, irq, cts, rts, sin, sout);
| Signal | Description |
| reset | This signal is normally connected to the
system reset signal. It resets the uart forcing it to the idle state,
setting the fifos to the empty state, and clearing any over run or framing
error. It also clears the interrupt enable bits and the request to send
output (rts).
reset is sampled on the positive edge of the clock |
| clk | this is usually connected to the system clock and is used as a base timing clock |
| ce | This is a system clock enable. Data will be latched into the uart on the rising edge of clk when ce is high. This signal may be tied high in systems where data is transfered from the system in a single clock cycle. |
| rd | This signal is used to signify a read operation to the uart. Note: the uart data outputs always reflect the contents of the currently addressed register regardless of the rd signal. However, the rd signal (combined with ce) is used to advance the receiver fifo. |
| wr | This signal is used to signify a write operation to the uart. |
| a | This is a three bit address vector used to address one of six available uart registers. (Registers are described below). |
| di | This is the data input bus to the uart. |
| do | This is the data output bus from the uart. |
| irq | This is an active high signal that indicates when an interrupt condition is present and interrupts are enabled. It will remain high until the interrupt condition is cleared. |
| cts | This is the clear to send (cts) input signal used for flow control. |
| rts | This is the request to send (rts) output signal used for flow control. |
| sin | This is the serial data input port. |
| sout | This is the serial data output port. |
Register Description
| Reg. No. | Function | Description |
| 0 | transmit / receiver buffer | write - write to transmit buffer (fifo) read - read from receive buffer (fifo) |
| 1 | status (read only) | bit 7 = interrupt bit 6 = received data present (check before reading reg. 0) bit 5 = receive buffer full bit 4 = transmit buffer empty bit 3 = transmit buffer full bit 0 = cts (clear to send) |
| 2 | control | bit 6 = receive data present - interrupt enable bit 5 = receive buffer full - interrupt enable bit 4 = transmit buffer empty - interrupt enable bit 1 = rts (request to send) output state |
| 3 | reset / error | a write to this register resets (clears) the
transmitter/receiver a read reads the error status bit 7 = receiver overrun bit 6 = receive char framing error |
| 4 | clock multiplier high | This register should be programmed with the high order byte
of the clock multiplier value.
The clock multiplier steps the 16x baud clock frequency in increments
of 1 / 65536 of the clk input using a harmonic frequency synthesizer |
| 5 | clock multiplier low | This register should be programmed with the low order byte of the clock multiplier value. |
| 6,7 | reserved | not used |
BC_UART_RX
The receiver module contains a three stage data input synchronizer on the serial data input in order to avoid meta-stability problems. If receiver over-run occurs due to data not being read from the receiver when the fifo is full, then incoming data bytes will be lost.
module bc_uart_rx(reset,
clk, baud16x_ce, rd, clear, do, sin, data_present, full, frame_err, over_run);
| Signal | Description |
| reset | This signal is normally connected to the
system reset signal. It resets the receiver by forcing the receiver state
machine to the idle state, setting the fifo to the empty state, and
clearing any over run or framing error.
reset is sampled on the positive edge of the clock |
| clk | this is usually connected to the system clock and is used as a base timing clock |
| baud16x_ce | This is the 16x baud rate clock enable. This clock enable is sampled on the rising edge of the clk signal, and it should only be a single clk pulse width wide to ensure proper operation. Timing of incoming data is determined from this clock. Each bit is sampled at 1/16 the baud16x_ce rate |
| rd | This signal is used to read data from the fifo. If data is present the fifo will advance to the next item after the read. The rd signal should be one clk pulse in width and is sampled on the positive edge of the clk signal. |
| clear | This signal performs the same function as
the reset signal. It is provided to allow resetting the receiver without
using the system reset signal. It resets the receiver by forcing the
receiver state machine to the idle state, setting the fifo to the empty
state, and clearing any over run or framing error.
clear is sampled on the positive edge of the clock. |
| do | This is the data output from the fifo. It always reflects the next available data byte. |
| sin | This is the serial data input port. It would normally be connected to an external physical interface such as an RS232 line receiver. There is a three stage synchronizer between this input and the receiver module to avoid meta-stability problems. |
| data_present | This signal indicates that there is data present in the fifo that is ready to be read. As soon as the data is read, this signal will be cleared. |
| full | This signal indicates that the receiver fifo is full. Any additional incoming data will result in over-run status and loss of data. |
| frame_err | This signal indicates a framing error in the incoming serial data stream due to the absence of a stop bit. |
| over_run | This signal indicates the receiver over-run state. Over-run occurs when the fifo is full and a new character is received. |
BC_UART_TX
module bc_uart_tx(reset, clk, baud16x_ce, wr, clear, di, sout, full, empty);
| Signal | Description |
| reset | This signal is normally connected to the
system reset signal. It resets the transmitter by forcing the transmitter
state machine to the idle state, and setting the fifo to the empty state.
reset is sampled on the positive edge of the clock |
| clk | this is usually connected to the system clock and is used as a base timing clock |
| baud16x_ce | This is the 16x baud rate clock enable. This clock enable is sampled on the rising edge of the clk signal, and it should only be a single clk pulse width wide to ensure proper operation. Timing of outgoing data is determined from this clock. Each bit is transmitted at 1/16 the baud16x_ce rate |
| wr | This signal is used to write data to the fifo. The fifo will automatically advance to the next item after the write. The wr signal should be one clk pulse in width and is sampled on the positive edge of the clk signal. |
| clear | This signal performs the same function as
the reset signal. It is provided to allow resetting the transmitter
without using the system reset signal. It resets the transmitter by
forcing the transmitter state machine to the idle state, and setting the
fifo to the empty state,.
clear is sampled on the positive edge of the clock. |
| di | This is the data byte input to the fifo. |
| sout | This is the serial data output port. It would normally be connected to an external physical interface such as an RS232 line driver. |
| full | This signal indicates that the transmitter fifo is full. Additional data written to the transmitter when the fifo is already full will overwrite the current contents of the fifo. |
| empty | This signal indicates that the transmitter fifo is empty. |