vgavic Core

2010 Robert Finch

Overview

vgavic is a video interface circuit for use within a SoC to interface the system to a VGA compatible display device. The exact capabilities depend on the characteristics of the system it is used in (memory bandwidth, memory capacity, clock frequency).

VGA Video Interface Circuit with the following features:

Text Mode

Text mode supports up to 65536 different character glyphs / codes. The maximum glyph code may be set in a register (reg. 13)  to prevent the controller from accessing memory outside of the glyph table when a limited number of glyphs are used. Each character in text mode has a foreground and background color. Text memory has the following layout. It is possible to map the entire screen with different text mode characters, program the glyphs, and use text mode as if it were an additional bit-mapped mode. In this mode each bit in the glyph represents one of two different colors, determined from the text mode cell. The color depth may be set for text mode up to four bits per pixel. In this case the first two colors are read from the text mode cell, the remaining colors are determined from the color palette. The bits in a glyph are grouped together when the color depth is set greater than one bit per pixel. Text mode determines the screen address in memory from the video memory address register.

The glyph width may also be controlled. However setting the glyph width too low will result in display problems as the controller will be unable to fetch data from memory at the resulting fetch rate. Glyph width may be set up to sixteen pixels. The controller reads either a byte or a half-word (sixteen bits) as needed for the glyph. The default glyph width is set to seven pixels. When oddball glyph widths are chosen (not 8/16) extra bits in the byte / half-word are discarded.

Glyph height may also be controlled by bits in register 2. The controller assumes a limited number of memory layouts for glyphs in order to simplify the address calculation. The glyph table is either one or two bytes wide, and either eight or sixteen scan lines deep for each glyph. The glyph is pulled from memory cells as needed. A 12 x 12 character glyph will use 32 bytes of memory (16 bits by 16 scan lines). The default height is eight scan lines.

Text Mode Cell

Color Codes

Foreground and background color bytes

Bitmapped Mode

Bitmapped mode displays memory in linear sequence. Bits are grouped as a unit to represent colors as needed for the selected color depth. For color depths less than five bits per pixel, the bit group indexes into the color palette area to determine which color to display. When six bits or more are selected for the color depth the bits directly represent RGB values, with two bits each for red, green and blue.

Mixed Mode

It is possible to have the controller switch from bitmapped mode to text mode automatically at any scan line of the display.

Smooth Scrolling

Both the border area, and the memory fetch region may be controlled by registers in the controller. Changing the border area without changing the fetch area will result in some characters being hidden from the screen. By combining this with modification of the memory fetch region, smooth scrolling can be effected. Note that memory fetch must normally begin a number of pixels (depending on the video mode) before display occurs. This is due to pipelining in the video controller (the controller has to have the data available in its pipeline before it can start displaying it).

Display enable - there is a global display enable that may be used to disable display output and corresponding memory fetches.

Sprites

Sprites are image areas that may be controlled independently from the remainder of the screen. Sprites are available in all display modes. Sprites normally appear in front of other images on the screen. However if bit 6 (the sprite priority bit) of the screen color is set, the sprite will appear behind these colors. Sprites may also be designated as alpha blenders, in this case the low order two bits of the color determine the amount of blending 0 = black, 1 = 33%, 2 = 66% and 3 = 100%.

The video controller contains a up to 4kB dual port memory to contain the sprite image data. This may be mapped into the SoC using a separate chip select. Each sprite image is allocated 512 bytes of memory.

Display Priority

Sprites have a fixed display priority with respect to one another. Sprite 0 appears in front of all other sprites, Sprite 1 has the next highest priority and so on down the line. Sprites appear behind pixels where bit 6 of the pixel color is set to zero, otherwise they appear in front of other pixel colors. However sprites also appear in front of the color defined as the background color. The background color is set in the background color register (register 12).

Format

Both the width and the height of the sprite may be set by setting values in the sprite width and height registers. The product of the width and height should not exceed 511. Both the width and height may vary from 1 to 63 pixels. Sprites default to a size of 24 x 21 for width and height respectively. Sprite may be made either double width or double height or both double width and double height. For double width or double height the size of the displayed pixels is doubled (there are still the same number of pixels for the sprite, they are just twice as large). Sprites may be positioned at any location on (or off) the screen. They will be clipped by the border.

Timing Controls

VGA timing characteristics are completely programmable. However the critical timing controls are locked by default. Timing is set up for a standard 640 x 480 VGA display. In some circumstances it may be necessary to change the timing controls, for instance in order to support a higher resolution display.

Memory Addressing / Memory Bandwidth Usage

This core assumes that the memory system will be able to provide data at a high enough rate so that a line buffer is unnecessary. Video memory access is pipelined and buffered so that a request for more data begins when the data in the last stage of the pipeline has been used. The pipeline provides data needed for display. As the pipeline is supplying the data more data is being supplied to the pipeline by the memory system. Generally, it will take several clock cycles for the controller to use the current data of the last pipeline stage; the memory system must be able to supply new data within this window. For instance, in 40 x 25 text mode with a 28MHz clock there are 16 clock cycles within which to fetch new data. In this time frame the controller needs to perform 3 memory reads. In 320 x200 x 6 bpp the controller needs to read from memory once every four clock cycles.

Register Description