ts_timer System Time Slicer
2010 Robert Finch
Overview
ts_timer is a core designed for implementing a simple system time slice timer or watchdog timer. It has a programmable timeout from 1 to 256 milliseconds in one millisecond increments. It has both a level sensitive interrupt output which can be disabled, and a time-out output that pulses high for a single cycle on each timeout.
The core can easily be interfaced to an SoC bus. It is WISHBONE compatible.
Notes:
The one millisecond timer interval is generated by dividing the input clock frequency down using a 17 bit linear feedback shift register counter (LFSR). The LFSR is coded assuming a 28.636 MHz clock frequency. The LFSR value (a constant) of the LFSR will have to be changed to accommodate different clock frequencies. This can be set by specifying a parameter for the LFSR count. The LFSR "free runs" and is not affected by reset. On initial startup the LFSR will not provide an accurate 1ms interval for the first interval. It may require 128k clock cycles before the LFSR locks into a 1ms pattern (for example 32,768 clocks = 1.6ms @ 20MHz),
Download ts_timer.v
Signal Description
module ts_timer(rst, clk, ce, cyc, cs, wr, adr, din, dout, ack, irq, tout);
parameter pLFSR;
parameter pMaxCount;
All signals are active high unless otherwise noted.
| Signal | Description |
| rst | This signal is normally connected to the system reset signal. It resets the timer forcing the current count to zero, disables the interrupt output and clears the timeout output. |
| clk | this is usually connected to the system clock and is used as a base timing clock |
| ce | This is a core clock enable. It allows the core to operate at a lower clock rate than the system clk signal. Data will be latched into the timer on the rising edge of clk when ce is high. |
| cyc | This signal indicates that a valid bus cycle is taking place. The core will not respond to the bus unless this signal is active. |
| cs | Core select. Enables updating the timer registers. Note: the timer data outputs always reflect the contents of the currently addressed register |
| wr | This signal is used to signify a write operation to the timer. |
| adr | This is a single bit address used to address one of two available timer registers. (Registers are described below). |
| din | This is the data input bus to the timer (eight bits). |
| dout | This is the data output bus from the timer (eight bits). |
| ack | This signal indicates that the core has processed the bus transaction (it is the logical and of cyc, ce, and cs). |
| irq | This is an active high signal that indicates when an interrupt condition is present and interrupts are enabled. It will remain high until the interrupt condition is cleared (by writing the timer control register). |
| tout | This is the timeout output from the timer. This output pulses high for a single cycle each time the timeout occurs. |
| Parameters | |
| pLFSR | This is a seventeen bit constant used to control a LFSR counter that generates one millisecond pulses. The LFSR value needs to be set differently for different clock frequencies. An LFSR calculator or lookup table will need to be used to figure out the required value. The default setting $169AB sets a 1ms timeout assuming a 28.636MHz clock. |
| pMaxCount | This is the default timeout register setting. It has a value of 20 for 20 milliseconds. |
Register Description
| Reg. No. | Function | Description |
| 0 | timeout value | read / write - timer timeout value in milliseconds (timeout=n+1 ms) |
| 1 | status / control | Write:
bit 0 = interrupt enable, 1 = inhibit interrupt, 0 = enable interrupt bit 1 = interrupt state, 1 = force irq, 0 = clear irq Read: bit 0 = interrupt enable state, 1 = interrupts inhbited, 0 = interrupts enabled bit 1 = interrupt state, 1 = interrupt active, 0 = no interrupt |
WISHBONE Compatibility Datasheet
The ts_timer core may be directly interfaced to a WISHBONE compatible bus. When interfaced to a WISHBONE bus the clock enable signal (ce) should be tied high.
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WISHBONE Datasheet WISHBONE SoC Architecture Specification, Revision B.3 |
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Description: |
Specifications: |
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General Description: |
system time slice timer |
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Supported Cycles: |
SLAVE, READ / WRITE SLAVE, BLOCK READ / WRITE SLAVE, RMW |
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Data port, size: Data port, granularity: Data port, maximum operand size: Data transfer ordering: Data transfer sequencing |
8 bit 8 bit 8 bit Little Endian any (undefined) |
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Clock frequency constraints: |
none |
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Supported signal list and cross reference to equivalent WISHBONE signals |
Signal Name: ack adr clk din(7:0) dout(7:0) cyc cs wr |
WISHBONE Equiv. ACK_O ADR_I() CLK_I DAT_I() DAT_O() CYC_I STB_I WE_I
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Special Requirements: |
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