Downloads

Raptor64.zip (download not working yet)

General Purpose Registers

The Raptor64 has 32 general purpose registers, although four registers have special uses. R0 always reads as the value zero. R31 is the subroutine link register (LR). The call instruction automatically updates this register with the return address of a subroutine. This register is also used implicitly by the return instruction. R30 is the stack pointer (SP) register. The return instruction automatically updates this register. R29 references the program counter for the instruction and may be used to form program counter relative addresses. R29 is a read-only register.

Segmentation Registers

Raptor64 has 16 segment registers. For data addresses the segment register is chosen by the most significant four bits of the address. For example an address like 0xE000000000000010 uses segment register #14 because the upper nibble of the address is an 'E'. Note that segmentation does not apply to I/O addresses. I/O instructions 'in' and 'out' do not use segmentation; only load and store instructions use it.

For code addresses segment register #15 is always used unless the upper nibble of an address is 'F' in which case segmentation is ignored. This allows the operating system code located in the memory region 0xFxxxxxxxxxxxxxxx to run without paying attention to segmentation. An alternate name for segment register #15 is the CS (code segment) register.

There are four instructions supporting segment registers. Mtseg - move to segment register, mtsegi - move to segment register indirect, mfseg - move from segment register and mfsegi - move from segment register indirect.

The segment register is added (without a shift) to the effective address to form a final segmented address. Some of the low order bits of the segment register are always zero.

Execution Pattern Table

The execution pattern table is a 256 entry table that contains context id's. The processor periodically cycles through the execution pattern table to determine which register set context to use. For the non-hyper threading CPU the iepp instruction is used to cycle through the table. This instruction will typically be called from a timer interrupt service routine. The hyper-threading CPU automatically cycles through the execution pattern table. The execution pattern table can be used to control the frequency with which particular contexts are executed. Higher priority contexts can be given more slots in the execution pattern table which will result in the context being executed more frequently. Note that slot #0 of the 256 slots is always zero. This means that context #0 is guarenteed to always execute. Additionally, the execution pattern table is initialized to zero on reset, meaning that context zero is the only executing context. The execution pattern table is updated and read using the mfep - move from execution pattern, and mtep - move to execution pattern table instructions.

Simple MMU

Overview

The SimpleMMU provides simple memory management capabilities for the Raptor64 CPU. Memory management by the SimpleMMU includes virtual to physical address mapping. The SimpleMMU divides a 128MB memory space up into 512,  256kB pages and supports 32 tasks. Processor address bits 18 through 26 (the virtual address) are used as a nine bit index into a map table to find the physical address page.  The MMU remaps the nine address bits into a 10 bit value used as address bits 18 to 27 when accessing a physical address. The lower eighteen bits of an address pass through the MMU unchanged. Also passing through the MMU unchanged are address bits 28 to 63. It is assumed that in the system where the Simple MMU would be relevant, that some or all of the high order bits of an address would be left unconnected. I/O accesses are not mapped by the SimpleMMU and I/O addresses pass through the MMU unchanged.

Map Tables

The mapping table for memory management is stored directly in the SimpleMMU rather than being stored in main memory as is commonly done. The SimpleMMU directly supports up to 32 tasks. Each task has its own mapping table. The mapping table for only a single task is accessible at one time. Mapping table access is controlled by an access key. Eight MMU’s may be used in a system to allow up to 256 tasks.

Access Key

Access to the mapping table is controlled by an access key. The access key contains the task number for the mapping table to be accessed. The mapping table for only a single task may be accessed at one time. In order to access a map table for another task, the access key must be updated with the desired task number. The upper three bits of the access key identify the MMU to be updated or read from. The lower five bits of the access key identify the map table.

Operate Key

The operate key controls which map table (which task) is currently mapping addresses. The upper three bits of the operate key identify the MMU actively mapping addresses. The lower five bits select the map table within an MMU.

Key Value Register

The key value register is used to identify the MMU and is how the MMU’s are differentiated.  Operations on the MMU data are only possible if the key value register matches the high order three bits of the access key.

Mapping Table / Register Set:

The register set for the MMU is based at I/O address of $DC4000. The mapping table appears as a set of 1024 consecutive I/O locations. All mmu’s share a common register set occupying the same I/O address range, with the exception of the key value register. Access to a particular mmu is controlled by the top three bits of the access key.

The top three bits of the access key must match the key value register in order to read/write the register set. Also, the ‘s’ bit must be set.

The lower five bits of the access key select the map for one of thirty-two tasks.

The operate key determines which task is the task actively mapping the address space.

The MMU divides memory up into 512  256k pages. Address bits 18 through 26 index into a map table to find the physical address page.

Kernel Mode and the ‘s’ bit.

Transitioning into Kernel mode causes the ‘s’ bit to be set. This results in the MMU using task#0 to map addresses. The processor transitions into Kernel mode when a hardware interrupt or software exception occurs. In order to allow other tasks to map addresses, the countdown fuse must be set. When the countdown expires (it has to reach -1) the ‘s’ bit is cleared, and the task identified by the operate key controls memory mapping. The only way to clear the ‘s’ bit is by setting the countdown fuse. The ‘s’ bit is contained in a read-only register.

Tasks

Task #0 is assumed to be the system task. Task #1 is assumed to be the DMA task. When the cpu transitions into kernel mode, task #0 is selected as the map controller. The ‘s’ bit is set which forces task #0 to map addresses. The task actively mapping addresses is controlled by the operate key when the ‘s’ bit is not set.

Address Pass-through

Addresses pass through the MMU unaltered until the mapping enable bit is set. Until mapping is enabled, the physical address will match the virtual address. Additionally address bits 0 to 17 pass through the MMU unaltered. Address bits 28 to 63 pass through the MMU unaltered as well.

Raptor64 Instruction Set