BC6502
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Download: bc6502.zip
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WISHBONE Datasheet WISHBONE Soc Architecture Specification, Revision B.3 Description: |
Specifications: | |
| General Description | Eight bit microprocessor | |
| Supported Cycles:
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MASTER,READ/WRITE MASTER,BLOCK READ/WRITE MASTER,RMW |
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Data port, size: Data port, granularity: Date port, maximum operand size: Data transfer ordering: Data transfer sequencing: |
8 bit 8 bit 8 bit Undefined Undefined |
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| Clock frequency contraints: | none | |
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MASTER Port cross reference to equivalent WISHBONE Signals |
Core | WISHBONE |
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ack_i adr_i(15:0) clk_i rst_i dat_i(7:0) dat_o(7:0) cyc_o stb_o we_o |
ACK_I ADR_I CLK_I RST_I DAT_I DAT_O CYC_O STB_O WE_O |
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| Special Requirements: | ||